{"portal":"Timmyless Talent — UK Analog Design Engineers","generatedFrom":"public professional sources","count":47,"candidates":[{"id":"matthew-schormans","name":"Matthew Schormans","headline":"Analog IC Design Engineer","seniority":"Senior","location":"Cambridge, England","region":"Cambridge","yearsExperience":"3–7","currentRole":"Senior Analog IC Design Engineer","currentEmployer":"Intrinsic","previousEmployers":[],"education":["UCL"],"skills":["Analog IC design","Cambridge semiconductor ecosystem"],"domains":["Analog IC","Mixed-Signal"],"availability":"Currently at Intrinsic; approachable via public profile","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/matthew-schormans-19265520a"},{"type":"Job board listing","url":"https://rocketreach.co/matthew-schormans-email_732656389","note":"Public directory snippet — role/location confirmation"}],"notes":"Senior analog IC designer in the Cambridge cluster; ex-Intrinsic role listed alongside prior positions (4+ on profile).","discoveredAt":"2026-10-29"},{"id":"swetha-l","name":"Swetha L.","headline":"Mixed Signal IC Design Engineer — actively open to roles","seniority":"Mid-level","location":"United Kingdom","region":"England (not specified)","yearsExperience":"3","currentRole":"Analog / Mixed-Signal IC Design Engineer","currentEmployer":"Open to roles (stated on profile)","previousEmployers":[],"education":[],"skills":["Analog IC design","RF","Mixed-Signal"],"domains":["Analog IC","RF","Mixed-Signal"],"availability":"Explicitly states: open to roles in analogue/RF/mixed-signal IC design","openToWork":true,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/swetha-l-2748a717b"}],"notes":"Three years industry experience; profile explicitly invites analogue/RF/mixed-signal roles — strong active candidate.","discoveredAt":"2026-10-29"},{"id":"penny-gould","name":"Penny Gould","headline":"Senior Analog IC Design Engineer","seniority":"Senior","location":"Lechlade-on-Thames, England","region":"South West / Thames Valley","yearsExperience":"10+","currentRole":"Senior Analog IC Design Engineer","currentEmployer":"HiLight Semiconductor Ltd","previousEmployers":[],"education":["King's College London"],"skills":["Analog IC design","Silicon photonics driver/sensor ICs (HiLight domain)"],"domains":["Analog IC"],"availability":"At HiLight Semiconductor; passive candidate","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/penny-gould-icdesigner"}],"notes":"Senior analog IC designer at HiLight (Oxfordshire photonics IC scene); KCL educated.","discoveredAt":"2026-10-29"},{"id":"stephen-ogunniran","name":"Stephen Ogunniran","headline":"Principal Analog Verification Engineer @ Mach42 | PMIC design background","seniority":"Staff / Principal","location":"London, England","region":"London","yearsExperience":"8+","currentRole":"Principal Analog Verification Engineer","currentEmployer":"Mach42","previousEmployers":["Crypto Quantique (Senior Analog IC Designer, 2019–2021)"],"education":["MSc Analog and Digital IC Design"],"skills":["PMIC design","Switched-capacitor analog","High-precision analog","Analog verification"],"domains":["Power Management (PMIC)","Analog verification"],"availability":"Employed; strong verification + design dual profile","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/stephen-ogunniran-a93313a3"}],"notes":"Custom PMIC chip design background, now principal-level analog verification — valuable for design-adjacent QA roles too.","discoveredAt":"2026-10-29"},{"id":"colin-perry","name":"Colin Perry","headline":"Analog and Mixed-Signal Design Engineer","seniority":"Staff / Principal","location":"Swindon, England","region":"South West","yearsExperience":"25+","currentRole":"Analog and Mixed-Signal Design Engineer","currentEmployer":"Independent / available (long career since GEC Plessey era)","previousEmployers":["GEC Plessey Semiconductors (1991–1998)"],"education":[],"skills":["Analog IC design","Mixed-signal design","Research background"],"domains":["Analog IC","Mixed-Signal"],"availability":"Deep veteran pool — approach directly","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/colin-perry-uk"}],"notes":"Career analog designer from the Swindon semiconductor lineage (GEC Plessey alumni); research experience noted on profile.","discoveredAt":"2026-10-29"},{"id":"diego-golpe-molinos","name":"Diego Golpe Molinos","headline":"Senior Analog IC Designer (Synopsys)","seniority":"Senior","location":"Plymouth, England","region":"South West","yearsExperience":"8+","currentRole":"Senior Analog IC Designer","currentEmployer":"Synopsys Inc","previousEmployers":["4+ prior companies (per public profile)"],"education":["Tecnun — Universidad de Navarra"],"skills":["Analog IC design","Design IP / reference designs"],"domains":["Analog IC"],"availability":"At Synopsys; passive candidate","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/diego-golpe-molinos-054b0b114"}],"notes":"551+ connections; Spanish-educated senior designer based in Plymouth working for Synopsys UK.","discoveredAt":"2026-10-29"},{"id":"meraj-ahmad","name":"Dr Meraj Ahmad","headline":"Principal Analog/Mixed-Signal IC Design Engineer @ Neuranics | 4 tape-outs","seniority":"Staff / Principal","location":"Glasgow / Edinburgh region, Scotland","region":"Scotland","yearsExperience":"8+","currentRole":"Principal Analog/Mixed-Signal IC Design Engineer","currentEmployer":"Neuranics Ltd","previousEmployers":["University of Glasgow (Affiliate Researcher / Postdoc)"],"education":["University of Glasgow (PhD)"],"skills":["Analog & mixed-signal VLSI","Magnetic sensor interface ASICs","Neuromorphic hardware","Embedded systems","Tape-out delivery"],"domains":["Sensor interface ASICs","Neuromorphic","Mixed-Signal"],"availability":"Principal level; research-strong (49 publications, 572 citations)","openToWork":false,"resumeUrl":"https://www.researchgate.net/scientific-contributions/Meraj-Ahmad-2222311942","sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/merajahmad"},{"type":"Google Scholar","url":"https://scholar.google.com/citations?user=zkX-iDIAAAAJ&hl=en"},{"type":"ResearchGate","url":"https://www.researchgate.net/scientific-contributions/Meraj-Ahmad-2222311942"}],"notes":"Delivered four tape-outs leading ASIC development for magnetic sensor interfaces at Neuranics; strong academic/industry hybrid.","discoveredAt":"2026-10-29"},{"id":"xinchao-ma","name":"Xinchao Ma","headline":"Senior Analog Design Engineer (ex-Cirrus Logic)","seniority":"Senior","location":"Edinburgh / Lothian, Scotland","region":"Scotland","yearsExperience":"5+","currentRole":"Senior Analog Design Engineer","currentEmployer":"Cirrus Logic (per headline history)","previousEmployers":["Cirrus Logic"],"education":["The University of Edinburgh"],"skills":["Analog design","Audio/mixed-signal ICs (Cirrus domain)"],"domains":["Analog IC","Audio"],"availability":"Edinburgh analog cluster talent","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/xma630"}],"notes":"Edinburgh-educated analog designer with Cirrus Logic experience — code-converter/PLL friendly.","discoveredAt":"2026-10-29"},{"id":"chris-duff","name":"Chris Duff","headline":"Principal Analog IC Design Engineer @ Semtech","seniority":"Staff / Principal","location":"Stansted / Essex, England","region":"East of England","yearsExperience":"15+","currentRole":"Principal Analog IC Design Engineer","currentEmployer":"Semtech","previousEmployers":[],"education":[],"skills":["Broadband MMIC design","RF & microwave","High-speed TIA (to 400 Gbit/s/channel)"],"domains":["MMIC","High-speed serial","RF"],"availability":"Principal at Semtech; passive","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/chris-duff-8b670bb"}],"notes":"Leads broadband MMIC design to 400 Gbit/s per channel — top-tier for optical/transimpedance work.","discoveredAt":"2026-10-29"},{"id":"pavlos-aidinidis","name":"Pavlos Aidinidis","headline":"Mixed Signal Design Engineer @ SECQAI","seniority":"Mid-level","location":"London, England","region":"London","yearsExperience":"3–7","currentRole":"Mixed Signal Design Engineer","currentEmployer":"SECQAI (quantum-safe hardware security)","previousEmployers":[],"education":["Aristotle University of Thessaloniki (AUTH)"],"skills":["Mixed-signal design","Hardware security (PQC context)","Dual-use semiconductors"],"domains":["Mixed-Signal","Hardware security"],"availability":"500+ connections; at SECQAI","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/pavlos-aidinidis-0b8480160"},{"type":"Job board listing","url":"https://www.secqai.com/","note":"Employer site for context"}],"notes":"Mixed-signal engineer inside London's quantum-security hardware scene.","discoveredAt":"2026-10-29"},{"id":"darren-holdstock","name":"Darren Holdstock","headline":"Electronic Design Engineer — analogue & digital hardware speciality","seniority":"Senior","location":"England","region":"South East (not specified)","yearsExperience":"20+","currentRole":"Electronic Design Engineer","currentEmployer":"Independent / experienced hands-on designer","previousEmployers":[],"education":[],"skills":["Analogue hardware design","Digital hardware","Hardware troubleshooting (speciality)"],"domains":["Board-level analog","Embedded hardware"],"availability":"Long-experience board-level analog talent","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/darren-holdstock-a658286"}],"notes":"Best fit where 'analog design engineer' means board/instrumentation analog rather than IC; many years hardware design and development.","discoveredAt":"2026-10-29"},{"id":"nigel-kirkwood","name":"Nigel Kirkwood","headline":"RF IC Designer @ Semtech","seniority":"Senior","location":"Gloucester, England","region":"South West","yearsExperience":"15+","currentRole":"RF IC Designer","currentEmployer":"Semtech","previousEmployers":[],"education":[],"skills":["RF IC design","Wireless/transceiver blocks"],"domains":["RF IC","Wireless"],"availability":"Passive; long tenure","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/nigel-kirkwood-46695842"}],"notes":"Experienced RF IC designer at Semtech — LoRa/wireless RF block expertise.","discoveredAt":"2026-10-29"},{"id":"amine-tagant","name":"Amine Tagant","headline":"RF IC Design Engineer (ex-MediaTek UK)","seniority":"Mid-level","location":"Maidstone / South East England","region":"South East","yearsExperience":"3–5","currentRole":"RF IC Design Engineer","currentEmployer":"Formerly MediaTek (Maidstone) — 3.5 years","previousEmployers":["MediaTek"],"education":[],"skills":["RF IC design","Transceiver blocks","Silicon proven (MediaTek mobile RF)"],"domains":["RF IC","Mobile"],"availability":"Post-MediaTek — likely open to UK roles","openToWork":true,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/aminetagant"}],"notes":"3.5 years RF IC design at MediaTek Maidstone — proven mobile-RF silicon experience.","discoveredAt":"2026-10-29"},{"id":"jake-greene","name":"Jake Greene","headline":"Principal RF IC Design Engineer @ Vaire Computing","seniority":"Staff / Principal","location":"Cambridge, England","region":"Cambridge","yearsExperience":"10+","currentRole":"Principal RF IC Design Engineer","currentEmployer":"Vaire Computing","previousEmployers":[],"education":["University of East London"],"skills":["RF IC design","60 GHz / wireless","Startup silicon delivery"],"domains":["RF IC","Wireless"],"availability":"Principal level at Cambridge fabless startup","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/jake-greene-62817028"}],"notes":"500+ connections; principal RF IC engineer in the Cambridge startup ecosystem (Vaire — high-density wireless).","discoveredAt":"2026-10-29"},{"id":"zeeshan-ali","name":"Zeeshan Ali","headline":"Analog/RF IC Designer @ Semtech (data-centre ICs)","seniority":"Mid-level","location":"Stansted / Essex, England","region":"East of England","yearsExperience":"3–7","currentRole":"Analog/RF IC Designer","currentEmployer":"Semtech (joined early 2025)","previousEmployers":[],"education":[],"skills":["Analog IC design","RF IC design","Data-centre interconnect ICs"],"domains":["Analog IC","RF IC","Optical comms"],"availability":"Recently moved to Semtech for data-centre IC work","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/zeeshan-ali-94a5831b2"}],"notes":"Profile states IC design for data centres (TIA/driver domain at Semtech Stansted).","discoveredAt":"2026-10-29"},{"id":"saravanan-kathiah","name":"Saravanan Kathiah","headline":"Principal RF IC Design Engineer — 18 years analog/RF IC","seniority":"Staff / Principal","location":"Cambridge region, England","region":"Cambridge","yearsExperience":"18","currentRole":"Principal RF IC Design Engineer","currentEmployer":"Cambridge-area IC design house","previousEmployers":[],"education":[],"skills":["LNA","Mixer","AGC","Frequency synthesizer","RF transceiver system design"],"domains":["RF IC","Transceivers","Frequency synthesis"],"availability":"Deep principal pool","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/saravanankathiah"}],"notes":"18 years analog/RF IC design across transceiver chains — synthesiser, LNA, mixer, AGC ownership.","discoveredAt":"2026-10-29"},{"id":"vasileios-mylonakis","name":"Vasileios Mylonakis","headline":"Staff Engineer, Analogue/RF IC Design @ Qualcomm","seniority":"Staff / Principal","location":"Greater Cambridge Area, England","region":"Cambridge","yearsExperience":"10+","currentRole":"Staff Engineer, Analogue/RF IC Design","currentEmployer":"Qualcomm","previousEmployers":[],"education":[],"skills":["Analogue IC design","RF IC design","Mobile platform blocks"],"domains":["Analog IC","RF IC"],"availability":"Staff at Qualcomm Cambridge — passive","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/vasileios-mylonakis-9431a254"}],"notes":"Qualcomm Cambridge staff-level analogue/RF designer; flagship pay benchmarks apply (£57k–£104k+ band at this level per market data).","discoveredAt":"2026-10-29"},{"id":"nikunj-gandhi","name":"Nikunj Gandhi","headline":"PMIC Design Engineer — 15+ years analog & digital circuit design","seniority":"Senior","location":"United Kingdom (England)","region":"England (not specified)","yearsExperience":"15+","currentRole":"PMIC Design Engineer","currentEmployer":"UK PMIC design house","previousEmployers":[],"education":[],"skills":["Power management IC design","Analog circuit design","Digital circuit design"],"domains":["Power Management (PMIC)"],"availability":"States interest in state-of-the-art PMIC design roles","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/nikunj-gandhi-a582a716"}],"notes":"15+ years analog+digital with explicit PMIC focus — regulators, converters, references.","discoveredAt":"2026-10-29"},{"id":"patrick-ying-wu","name":"Patrick (Ying Wu)","headline":"Senior Staff IC Design Engineer — ADC/DAC, references, LDO","seniority":"Staff / Principal","location":"United Kingdom (England)","region":"England (not specified)","yearsExperience":"12+","currentRole":"Senior Staff IC Design Engineer","currentEmployer":"UK IC design house","previousEmployers":[],"education":[],"skills":["ADC","DAC","Voltage reference","LDO","Power management","Mixed-signal design"],"domains":["Data Converters","Power Management (PMIC)","Mixed-Signal"],"availability":"Senior staff — design ownership of full AMS block set","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/patrick-ying-wu-34989016"}],"notes":"Design, layout AND testing of power-management/mixed-signal/analog IC — rare full-flow ownership.","discoveredAt":"2026-10-29"},{"id":"filipe-ramos","name":"Filipe Ramos","headline":"Principal IC Design Engineer — PMIC","seniority":"Staff / Principal","location":"Cambridge region, England","region":"Cambridge","yearsExperience":"15+","currentRole":"Principal IC Design Engineer","currentEmployer":"UK PMIC design group","previousEmployers":["Founding engineer of a deployed IC design group (per profile)"],"education":[],"skills":["PMIC design","Team building / founding engineer","Power management ICs"],"domains":["Power Management (PMIC)"],"availability":"Principal; group-building experience suggests lead-readiness","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/fgrramos"}],"notes":"First employee of an IC design group deployed in a new location — strong candidate for founding analog/PMIC roles.","discoveredAt":"2026-10-29"},{"id":"billy-tomas","name":"Billy Tomas","headline":"Analogue IC Design & Verification Flow FAE | ex-transistor-level designer","seniority":"Senior","location":"United Kingdom","region":"England (not specified)","yearsExperience":"10+","currentRole":"FAE — Analog design & verification flows","currentEmployer":"EDA/vendor-facing technical role","previousEmployers":["Power Management IC R&D team"],"education":[],"skills":["Transistor-level IC design","Verification flows","PMIC R&D","Customer-facing technical support"],"domains":["Power Management (PMIC)","Design flows / EDA"],"availability":"Currently FAE-side; design-rooted","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/billytomas"}],"notes":"Started as transistor-level IC designer, now EDA-adjacent FAE — excellent for design-flow ownership and tooling-aware hires.","discoveredAt":"2026-10-29"},{"id":"oliver-beard","name":"Oliver Beard","headline":"Analogue IC Designer — Senior designer at Intrinsic Semiconductor","seniority":"Senior","location":"Cambridge, England","region":"Cambridge","yearsExperience":"5+","currentRole":"Senior Analogue IC Designer","currentEmployer":"Intrinsic Semiconductor Ltd","previousEmployers":[],"education":["Electronics engineering degree"],"skills":["Analogue IC design","Delivering design blocks to production"],"domains":["Analog IC"],"availability":"At Intrinsic; Cambridge passive candidate","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/oliver-beard-5812091a6"}],"notes":"Profile: 'electronics engineer with a passion for design, particular experience delivering...' — production-delivery focused.","discoveredAt":"2026-10-29"},{"id":"mario-iannazzo","name":"Mario Enrique Iannazzo Soteras","headline":"Analog IC Design Engineer — international PhD, nanoelectronics researcher","seniority":"Mid-level","location":"United Kingdom","region":"England (not specified)","yearsExperience":"7 (academic research) + industry","currentRole":"Analog IC Design Engineer","currentEmployer":"UK IC design / research","previousEmployers":[],"education":["PhD in Electronics (international)","Telecommunications engineering degree"],"skills":["Analog IC design","Nanoelectronics","Device modelling research"],"domains":["Analog IC","Advanced nodes / devices"],"availability":"PhD-level depth, engineering output","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/marioiannazzo"}],"notes":"7 years academic research in nanoelectronics plus IC design engineering — strong for advanced-node analog.","discoveredAt":"2026-10-29"},{"id":"siwen-liang","name":"Siwen Liang","headline":"RF/Analogue IC Design Engineer @ Analog Devices (14 years)","seniority":"Staff / Principal","location":"Edinburgh region, Scotland","region":"Scotland","yearsExperience":"14+","currentRole":"RF/Analogue IC Design Engineer","currentEmployer":"Analog Devices","previousEmployers":["Cascoda Ltd (Analogue IC Design Engineer, 2010–2012)"],"education":[],"skills":["RF IC design","Analogue IC design","MEMS/RF (Cascoda background)"],"domains":["RF IC","Analog IC"],"availability":"Long AD tenure — passive senior","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/siwen-liang-a0a23a14"}],"notes":"Analog Devices Edinburgh 14 years + Cascoda — rf/analog depth at the UK's flagship analog company.","discoveredAt":"2026-10-29"},{"id":"zhe-y","name":"Zhe Y.","headline":"Engineer @ Analog Devices | MSc Imperial College","seniority":"Graduate / Junior","location":"United Kingdom","region":"Scotland / South East (AD site dependent)","yearsExperience":"1–3","currentRole":"Engineer","currentEmployer":"Analog Devices, Inc.","previousEmployers":[],"education":["Imperial College London — MSc (CSP)"],"skills":["Signal processing","Electronics","Recent-graduate energy"],"domains":["Analog / mixed-signal engineering (early career)"],"availability":"Recent graduate — ideal junior/associate hire","openToWork":true,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/zhe-y-032655232"}],"notes":"Recent graduate with strong electronics/signal-processing interest, already at Analog Devices.","discoveredAt":"2026-10-29"},{"id":"snehil-verma","name":"Snehil Verma","headline":"Analog IC designer — public CV available (Cadence Virtuoso)","seniority":"Mid-level","location":"Currently US-based (Texas) — UK-eligible profile under review","region":"International (UK-relocatable)","yearsExperience":"3+","currentRole":"Analog design / VLSI engineer","currentEmployer":"US-based (Cockrell School alumni)","previousEmployers":[],"education":["Cockrell School of Engineering (MSc)"],"skills":["Cadence Virtuoso Analog Design Environment (IC 616)","Schematic design","Analog circuit design"],"domains":["Analog IC"],"availability":"Public CV with full contact + project detail","openToWork":true,"flag":"Not UK-confirmed — public-CV example; verify right to work before shortlisting","resumeUrl":"https://snehilverma41.github.io/Resume.pdf","sources":[{"type":"Personal site / public CV","url":"https://snehilverma41.github.io/Resume.pdf","note":"Downloadable public résumé PDF"},{"type":"Personal site / public CV","url":"https://snehilverma41.github.io/"}],"notes":"Included as a public-CV example: full downloadable resume, Virtuoso schematic work. Verify UK right-to-work before shortlisting.","discoveredAt":"2026-10-29"},{"id":"katarzyna-muszynska","name":"Katarzyna Muszynska","headline":"Senior Analogue IC Design Engineer","seniority":"Senior","location":"Greater Cambridge Area, England","region":"Cambridge","yearsExperience":"8+","currentRole":"Senior Analogue IC Design Engineer","currentEmployer":"Cambridge IC design house","previousEmployers":["Agile Analog (Analog IC Design Engineer, 2019–2020)"],"education":[],"skills":["Analogue IC design","Mixed-signal design & verification workflow","Analog design IP"],"domains":["Analog IC","Mixed-Signal","Design IP"],"availability":"Senior; Agile Analog (analog IP) pedigree — strong for reusable-block roles","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/katarzyna-muszynska-ba982761"}],"notes":"Cambridge-based senior analogue designer from Agile Analog (analog IP house) — mixed-signal design & verification workflow depth.","discoveredAt":"2026-10-29"},{"id":"tom-stanway-mayers","name":"Tom Stanway-Mayers","headline":"Analogue/Mixed-Signal IC Design Engineer (Intrinsic; ex-Lightmatter)","seniority":"Senior","location":"Cambridge, England","region":"Cambridge","yearsExperience":"5+","currentRole":"Analogue/Mixed-Signal IC Design Engineer","currentEmployer":"Intrinsic","previousEmployers":["Lightmatter (Senior Staff Analog IC Design Engineer, Mar 2024–May 2025)"],"education":[],"skills":["Analog IC design","Mixed-signal","Photonic-interconnect datacom ICs (Lightmatter domain)"],"domains":["Analog IC","Mixed-Signal","Optical comms"],"availability":"Currently Intrinsic; senior-staff experience at Lightmatter","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/tom-stanway-mayers-b5589282"}],"notes":"Progressed to Senior Staff Analog IC Designer at Lightmatter (photonics datacom) then Intrinsic — advanced-node analog for AI interconnect.","discoveredAt":"2026-10-29"},{"id":"andrea-mifsud","name":"Andrea Mifsud","headline":"Staff Mixed-Signal IC Design Engineer — neurostimulation / ReRAM / imaging","seniority":"Staff / Principal","location":"United Kingdom","region":"England (not specified)","yearsExperience":"8+","currentRole":"Staff Mixed-Signal IC Design Engineer","currentEmployer":"UK IC design (mixed-mode)","previousEmployers":[],"education":[],"skills":["Mixed-signal IC design","Neurostimulation front-ends","ReRAM","Image sensor readouts","Mixed-mode simulation"],"domains":["Mixed-Signal","Medical / implantable","Sensors"],"availability":"Staff level; niche analog front-end specialities","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/amifsud8"}],"notes":"Staff mixed-signal designer with neurostimulation, ReRAM and imaging analog-front-end experience — ideal for medical/sensor ASICs.","discoveredAt":"2026-10-29"},{"id":"harry-mclachlan","name":"Harry McLachlan","headline":"Mixed Signal Design Engineer @ Analog Devices (Edinburgh)","seniority":"Mid-level","location":"Edinburgh, Scotland","region":"Scotland","yearsExperience":"3–7","currentRole":"Mixed Signal Design Engineer","currentEmployer":"Analog Devices — Consumer Audio Solutions","previousEmployers":["Analog Devices (re-joined)"],"education":[],"skills":["Mixed-signal design","Consumer audio analog","Test & characterisation"],"domains":["Mixed-Signal","Audio"],"availability":"At AD Edinburgh; previously returned from other roles back to AD","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/harry-mclachlan-156934230"}],"notes":"Mixed-signal engineer in Analog Devices Edinburgh consumer-audio unit — mobile/audio codec domain.","discoveredAt":"2026-10-29"},{"id":"behzad-zeinali","name":"Behzad Zeinali","headline":"Analog Design Engineer (Apple) — low-power / low-noise building blocks","seniority":"Senior","location":"United Kingdom","region":"England (not specified)","yearsExperience":"8+","currentRole":"Analog Design Engineer","currentEmployer":"Apple (UK)","previousEmployers":[],"education":[],"skills":["Low-power analog","Low-noise analog","Power management","Data converter support blocks","High-performance analog"],"domains":["Analog IC","Power Management (PMIC)","Data Converters"],"availability":"Currently at Apple — high-calibre passive candidate","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/behzad-zeinali-4505b177"}],"notes":"Designs low-power/low-noise/high-performance analog building blocks including PMIC and data-converter support — Apple-grade depth.","discoveredAt":"2026-10-29"},{"id":"johannes-schiff","name":"Johannes Schiff","headline":"Principal Design Engineer @ Analog Devices — RF building blocks","seniority":"Staff / Principal","location":"United Kingdom","region":"Scotland / South East","yearsExperience":"15+","currentRole":"Principal Design Engineer","currentEmployer":"Analog Devices","previousEmployers":[],"education":[],"skills":["RF design","LNA","Active mixers","Very-low-power RF"],"domains":["RF IC","Analog IC"],"availability":"Principal at Analog Devices","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/johannes-schiff-73666a5"}],"notes":"Principal designer of very-low-power RF blocks (LNA, mixers) at Analog Devices — flagship analog company seniority.","discoveredAt":"2026-10-29"},{"id":"arash-abbasi","name":"Dr Arash Abbasi","headline":"Staff RFIC Design Engineer — analog & RF IC + silicon bring-up","seniority":"Staff / Principal","location":"United Kingdom","region":"England (not specified)","yearsExperience":"10+","currentRole":"Staff RFIC Design Engineer","currentEmployer":"UK RFIC design house","previousEmployers":[],"education":["PhD"],"skills":["Analog IC design","RFIC design","Chip testing & measurement / bring-up"],"domains":["RF IC","Analog IC"],"availability":"Staff; hands-on design + bench measurement","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/arash-abbasi-ph-d-72228349"}],"notes":"PhD-level staff RFIC/analog designer with hands-on chip test & measurement expertise — design-to-silicon-verification ownership.","discoveredAt":"2026-10-29"},{"id":"n-raja-sekhar","name":"N. Raja Sekhar","headline":"Analog Design Manager — AMS IC team leadership, PLL specialist","seniority":"Lead / Head","location":"United Kingdom","region":"England (not specified)","yearsExperience":"18+","currentRole":"Analog Design Manager","currentEmployer":"UK AMS IC design team","previousEmployers":["VLSI (2006–2008, low-phase-noise PLL)"],"education":["VLSI design"],"skills":["Analog/mixed-signal IC design","PLL / clocking","Team leadership","Technical management"],"domains":["Analog IC","Clocking / PLL","Management"],"availability":"Manager grade — candidate for analog team lead / head roles","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/n-raja-sekhar-08ab1011"}],"notes":"Experienced analog/mixed-signal IC manager with PLL / low-phase-noise clocking roots — right profile to stand up or lead an analog team.","discoveredAt":"2026-10-29"},{"id":"alberto-gomez-saiz","name":"Dr Alberto Gomez Saiz","headline":"Principal RF IC Design Engineer @ Quantum Motion | Imperial PhD candidate","seniority":"Staff / Principal","location":"Cambridge / London, England","region":"Cambridge","yearsExperience":"8+","currentRole":"Principal RF IC Design Engineer","currentEmployer":"Quantum Motion","previousEmployers":[],"education":["Imperial College London (PhD candidate)","Royal Commission 1851 Industrial Fellow"],"skills":["RF IC design","Quantum-control hardware","Analog front-ends for cryogenic control"],"domains":["RF IC","Quantum hardware","Analog IC"],"availability":"Principal at Quantum Motion; academic/industrial hybrid","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/albertogomezsaiz"}],"notes":"Principal RF IC engineer at Quantum Motion and 1851 Royal Commission Industrial Fellow — cutting-edge cryogenic/quantum control analog.","discoveredAt":"2026-10-29"},{"id":"jacob-l","name":"Jacob L.","headline":"Analog IC Designer @ Analog Devices — LDO, references, DC-DC","seniority":"Mid-level","location":"United Kingdom","region":"Scotland / South East","yearsExperience":"2–3","currentRole":"Analog IC Design Engineer","currentEmployer":"Analog Devices (Feb 2024–present)","previousEmployers":[],"education":[],"skills":["Power management IC design","LDO","Voltage reference","DC-DC converters"],"domains":["Power Management (PMIC)","Analog IC"],"availability":"Rising PMIC talent already at Analog Devices","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/jacob-l-91025110"}],"notes":"Analog IC designer at Analog Devices since 2024 with PMIC block skills (LDO, bandgap/voltage reference, DC-DC) — strong mid-level hire.","discoveredAt":"2026-10-29"},{"id":"tadas-cydzikas","name":"Tadas Cydzikas","headline":"Senior Analog Design Engineer @ Cirrus Logic","seniority":"Senior","location":"Edinburgh / Lothian, Scotland","region":"Scotland","yearsExperience":"8+","currentRole":"Senior Analog IC Design Engineer","currentEmployer":"Cirrus Logic","previousEmployers":[],"education":[],"skills":["Analog IC design","LDO / regulation","Mixed-signal","Productisation / de-risking"],"domains":["Analog IC","Audio / mixed-signal"],"availability":"Senior analog at Cirrus Logic Edinburgh cluster","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/tadascydzikas"}],"notes":"Senior analog IC designer at Cirrus Logic — resolved LDO drift issues and de-risked projects to tapeout; audio/mixed-signal focus.","discoveredAt":"2026-10-29"},{"id":"gabriel-franco","name":"Gabriel Franco","headline":"Sr. Design Engineer @ Qorvo — SOI RF & analog (12 yrs)","seniority":"Senior","location":"United Kingdom (Sandy / Loughborough)","region":"East Midlands","yearsExperience":"12+","currentRole":"Sr. Design Engineer / Technical Lead IC design","currentEmployer":"Qorvo","previousEmployers":[],"education":[],"skills":["SOI RF design","Analog circuit design","RFIC front-ends","Technical lead"],"domains":["RF IC","Analog IC","Front-end modules"],"availability":"Technical lead at Qorvo — RF FEM / mobile front-end domain","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/gabriel-franco-448919107"}],"notes":"12+ years SOI RF + analog IC design, technical lead at Qorvo — mobile RF front-end module expertise.","discoveredAt":"2026-10-29"},{"id":"jilu-john","name":"Jilu John","headline":"Senior Engineer @ Arm — power supply / low-power / automotive design","seniority":"Senior","location":"Cambridge, England","region":"Cambridge","yearsExperience":"6+","currentRole":"Senior Engineer","currentEmployer":"Arm","previousEmployers":[],"education":[],"skills":["Power supply design","High-speed design","Low-power design","Automotive-grade design"],"domains":["Analog / power","Automotive","Low-power"],"availability":"Senior at Arm — board/IC power & low-power design","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/jilu-john-a6a86317a"}],"notes":"Senior engineer at Arm designing power supplies, high-speed, low-power and automotive systems — strong adjacent analog/power profile.","discoveredAt":"2026-10-29"},{"id":"simon-kan","name":"Simon Kan","headline":"Senior Analogue, Mixed-Signal & RFIC Design — 20+ years","seniority":"Staff / Principal","location":"United Kingdom","region":"United Kingdom","yearsExperience":"20+","currentRole":"Senior Staff Analogue / Mixed-Signal & RFIC Design Engineer","currentEmployer":"Public profile (20+ yr IC veteran)","previousEmployers":[],"education":[],"skills":["RFIC design","Analog building blocks","Mixed-Signal","SoC / PHY interfaces","Power management","Image-sensor analog"],"domains":["Analog IC","RF IC","Mixed-Signal","Image Sensors","PHY"],"availability":"Deep analog/RF/PHY veteran across imaging, SoC, PHY and power","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/simonkan"}],"notes":"20+ years semiconductor innovation across imaging, SoC, PHY, RFIC and power — rare broad senior analog generalist.","discoveredAt":"2026-10-29"},{"id":"vivek-mishra","name":"Vivek Mishra","headline":"RF / Analog Design Engineer @ Cambridge Silicon Radio (Qualcomm IPG)","seniority":"Mid-level","location":"Cambridge, England","region":"Cambridge","yearsExperience":"3–7","currentRole":"RF / Analog Design Engineer","currentEmployer":"Cambridge Silicon Radio","previousEmployers":[],"education":[],"skills":["RF front-end","Analog design","Bluetooth / wireless transceiver"],"domains":["RF IC","Analog IC","Wireless"],"availability":"RF/analog designer in the Cambridge cluster (CSR / Qualcomm)","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/vivek-mishra-8982ab24"}],"notes":"RF/analog design at Cambridge Silicon Radio (now Qualcomm IPG) — Bluetooth/wireless front-end domain.","discoveredAt":"2026-10-29"},{"id":"audrius-radvilas","name":"Audrius Radvilas","headline":"Staff Analog Design Engineer @ Analog Devices (Edinburgh)","seniority":"Staff / Principal","location":"Edinburgh, Scotland","region":"Scotland","yearsExperience":"10+","currentRole":"Staff Analog Design Engineer","currentEmployer":"Analog Devices","previousEmployers":[],"education":["University of Edinburgh"],"skills":["Analog IC design","Mixed-Signal","Data converters","Audio (ADI Edinburgh)"],"domains":["Analog IC","Mixed-Signal","Data Converters","Audio"],"availability":"Staff-level analog designer at ADI Edinburgh","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/audriusradvilas"}],"notes":"Staff Analog Design Engineer at Analog Devices, Edinburgh (Univ. of Edinburgh) — data-converter/audio analog pedigree.","discoveredAt":"2026-10-29"},{"id":"fahd-ben-abdeljelil","name":"Fahd Ben Abdeljelil","headline":"RFIC Design Engineer","seniority":"Mid-level","location":"United Kingdom","region":"United Kingdom","yearsExperience":"2–5","currentRole":"RFIC Design Engineer","currentEmployer":"RFIC design (UK)","previousEmployers":[],"education":[],"skills":["RFIC circuit design","IC layout","Verification methodology","IC simulators"],"domains":["RF IC","Analog IC"],"availability":"RFIC designer — public profile","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/fahd-ben-abdeljelil-aaa59613"}],"notes":"RFIC circuit design with IC-design tools/simulators and layout + verification methodologies.","discoveredAt":"2026-10-29"},{"id":"weizheng-wang","name":"Weizheng Wang","headline":"Graduate RFIC Design Engineer @ MediaTek UK (Imperial MEng)","seniority":"Graduate / Junior","location":"United Kingdom","region":"United Kingdom","yearsExperience":"1–3","currentRole":"Graduate RFIC Design Engineer","currentEmployer":"MediaTek UK","previousEmployers":[],"education":["Imperial College London (MEng EEE)"],"skills":["RFIC design","Wireless front-end","IC simulation"],"domains":["RF IC","Wireless"],"availability":"Early-career RFIC designer at MediaTek UK","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/weizhengwang"}],"notes":"Imperial MEng graduate, now graduate RFIC design engineer at MediaTek UK.","discoveredAt":"2026-10-29"},{"id":"haoyun-zhao","name":"Haoyun Zhao","headline":"Analog Design Engineer @ BYD — MSc Electronics (Edinburgh)","seniority":"Mid-level","location":"United Kingdom","region":"United Kingdom","yearsExperience":"3–7","currentRole":"Analog Design Engineer","currentEmployer":"BYD","previousEmployers":[],"education":["University of Edinburgh (MSc Electronics)"],"skills":["Analogue design","Mixed-Signal","Low-power analog"],"domains":["Analog IC","Mixed-Signal"],"availability":"Analog designer — verify current base / right-to-work before outreach","openToWork":false,"flag":"Listed on uk.linkedin; employer 'BYD' — confirm current location & work authorisation before contacting.","sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/haoyun-zhao"}],"notes":"MSc Electronics (Univ. of Edinburgh), analog design experience; UK index but employer cross-border — treat as verify-first.","discoveredAt":"2026-10-29"},{"id":"marios-c","name":"Marios C.","headline":"Analog Mixed-Signal IC DV Engineer @ Apple — ex-Nordic Semiconductor","seniority":"Mid-level","location":"United Kingdom","region":"Scotland","yearsExperience":"3+","currentRole":"Analog Mixed-Signal IC Design Verification Engineer","currentEmployer":"Apple","previousEmployers":["Nordic Semiconductor (2021)"],"education":[],"skills":["Mixed-Signal verification","Analog testbench","Verilog-A / AMS","Design-for-test"],"domains":["Mixed-Signal","Analog IC","Verification"],"availability":"AMS IC verification at Apple (ex-Nordic, Edinburgh)","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/marios-c-905213172"}],"notes":"Nordic Semiconductor (Nov 2021) → Apple Analog Mixed-Signal IC DV (Jun 2024) — strong AMS verification path.","discoveredAt":"2026-10-29"},{"id":"bekir-dogan","name":"Bekir Doğan","headline":"Principal Analog Design Engineer @ Renesas Electronics","seniority":"Staff / Principal","location":"United Kingdom","region":"United Kingdom","yearsExperience":"10+","currentRole":"Principal Analog Design Engineer","currentEmployer":"Renesas Electronics","previousEmployers":[],"education":["Boğaziçi University"],"skills":["Analog IC design","Mixed-Signal","Power management (PMIC)","PLL / clocking"],"domains":["Analog IC","Mixed-Signal","PMIC"],"availability":"Principal at Renesas UK (Swindon / Linlithgow)","openToWork":false,"sources":[{"type":"LinkedIn (public profile)","url":"https://uk.linkedin.com/in/bekir-dogan-911456105"}],"notes":"Principal analog design at Renesas Electronics UK — MSc/PhD-level 10+ yr analog/PMIC profile.","discoveredAt":"2026-10-29"}]}